MICS

Home
Research
People
Publications
Chip Gallery
Teaching
Links
Contact
Group only

3D-Integrated High-sensitivity Optical Receiver
Team member: Saman Saeedi

Increasing Silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this light, holistic design of high-speed optical links with an in-depth understanding of photonics and state-of-the-art electronics can bring their performance to unprecedented levels. In this project a 3D-integrated CMOS/Silicon-photonic receiver is presented. The electronic chip features a novel design that employs a low-bandwidth TIA front-end, double-sampling and equalization through dynamic offset modulation. We study different trade-offs in designing an optical receiver and how to choose between full-bandwidth TIA front-end and different integrating front-end architectures. The design methodology is supported by measurements of two 3D-integrated prototypes based on a conventional TIA and a double-sampling integrating receiver. The proposed receiver architecture achieves a sensitivity of -14.9dBm and energy efficiency of 170fJ/b at 25Gb/s.


Related Publications:

 © California Institute of Technology