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CMOS Receiver for Compressive Sensing
Team members: Juhwan Yoo, Matthew Loh and Manuel Monge


System block diagram

Since 1970, there has been a roughly thousand-fold improvement in computational power, made possible by reduction of transistor feature size. As a result, sensing and communications technology has increasingly relied on the use of sophisticated digital signal processing algorithms to improve performance and enhance reliability.

As signals in the phyiscal world are ultimately analog in nature, analog-to-digital converters (ADCs) are a key enabling technology for this trend. However, ADC speed and resolution have not kept pace with the stunning improvements in computing power, thus creating a bottleneck which limits the performance and application space of advanced signal processing techniques in physical systems.

In order to address this performance gap, we propose using the recently developed field of Compressed Sensing to build a system for very high speed wideband spectrum sensing and analysis. Compressed sensing is a particular instance of a broader class of techniques in statistics and estimation theory, known as Dimensionality Reduction techniques. In most situations of interest, the actual information that is sought is 'sparse', that is, it is contained in only a fraction of the acquired data. For example, in a spectral sensing problem, this sparsity is reflected by the fact that the frequency occupancy of the spectrum is small or highly structured. Compressed sensing leverages this sparsity by making assumptions about the type of data being acquired to intelligently undersample while retaining all the information of interest.

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