MICS

Home
Research
People
Publications
Chip Gallery
Teaching
Links
Contact
Group only

Research

Our research covers a wide range of topics in integrated circuits and systems. Our research group focuses on developing novel circuit (analog and digital) and system-level solutions for a variety of applications such as computing, communication, and sensors. The design of high-performance, reliable, and low-power mixed-mode circuits in highly-scaled technologies that leads to the advancement of the theory and the creation of new tools and models features among the goals of our research group.

Recent Projects

Silicon Photonics

  • Differential Ring Modulator (Click for more info)
  • In design of Micro-ring modulators it is desirable to have high-Q rings since for a given extinction ratio a higher Q results in better energy efficiency. However, there is a trade-off between the Q of the ring resonator modulator and its optical bandwidth. In this project we propose a new structure is proposed that breaks the optical bandwidth/quality factor trade-off known to limit the speed of high-Q micro-ring modulators. This structure, called the “differential ring modulator", maintains a constant energy in the ring to avoid pattern-dependent power droop.

  • PTAT Temperature Sensor for Micro-Ring Resonator Thermal Stabilization (Click for more info)
  • As the resonance wavelength of micro-ring modulators is susceptible to temperature fluctuations, they require thermal tuning. The power consumed by wavelength stabilization circuitry is often higher than the transmitter itself. In this project a monolithic PTAT temperature sensor is proposed for low-power thermal stabilization of micro-ring resonator modulators through direct measurement of temperature.


High-Speed Electrical & Optical Interconnects

  • WDM-Based Energy Proportional Parallel Optical Receiver (Click for more info)
  • Optical interconnects are essential components in data center networks. Energy proportional data centers can achieve significant power savings by reducing power consumption at lower data-rates or when idle. We use adaptive body biasing to present an energy proportional source-synchronous 4-channel WDM-based parallel optical receiver.

  • 3D-Integrated High-sensitivity Optical Receiver (Click for more info)
  • Increasing Silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this project a 3D-integrated CMOS/Silicon-photonic receiver is presented. The receiver is specifically designed to take advantage of low-cap 3D integration and advanced silicon photonics.

  • Ultra-Low-Power Equalization and Crosstalk Cancellation (Click for more info)
  • The increasing demand for high bandwidth interconnection between integrated circuits requires large numbers of I/Os per chip as well as high data rates per I/O. Key limitations in meeting these requirements include channel characteristics and I/O power consumption. Using receiver and transmitter equalization can greatly improve the link performance.

  • Low-Power Optical Interconnects (Click for more info)
  • The negligible frequency dependent loss of optical channels provides the potential for optical links to fully leverage increased data rates provided through CMOS technology scaling without excessive equalization complexity. A compact low-power optical receiver has been designed to explore the potential of optical signaling for future chip-to-chip and on-chip communication.

  • All-Digital Clock and Data Recovery (Click for more info)
  • As data rates increase, process, voltage and temperature variations cause sufficient phase mismatch between signal paths to require per-pin phase alignment - even in source-synchronous systems. This project involves the development of a novel all-digital clock and data recovery technique for per-pin phase adjustment in high-density, high-performance serial interconnect.

  • VCSEL driver

Circuits for Biological and Medical Systems

  • Origami Biomedical Implants (Click for more info)
  • Origami implant design is a 3D integration technique which addresses the size and cost constraints in biomedical implants. Large systems can be split into multiple chips and connected using 3D integration techniques to be folded compactly for implantation and unfolded inside the body. Electronics can be partitioned into functional blocks for mass-production and customs implants can be assembled from these relatively cheap modules.

  • Retinal Prosthesis (Click for more info)
  • Most progressive vision loss occurs when the first layer of the retina (the photoreceptors) is damaged. Retinal prostheses aim to restore vision by bypassing the damaged photoreceptors and directly stimulating the remaining healthy neurons. Our approach uses highly scaled technologies to reduce area and power, and to support hundreds of channels for fully intraocular implants.

  • Brain-Computer Interfaces (Click for more info)
  • Brain Protect

Sub-Nyquist Signal Acquisition Systems

RF/spectral sensing applications requiring multi-GHz bandwidths have typically relied on advances in ADCs to achieve enhanced performance, but such improvements are becoming increasingly difficult to achieve. The vast quantity of data collected by high sample rate ADCs poses a communication and processing challenge. However, most of the interesting signals are structured and contain less information than their overall spectral occupancy would indicate. This suggests that a sampling rate lower than Shannon-Nyquist rate can be used for certain applications.


On-Chip Communication Networks and Clocking

  • Low-power First-order Frequency Synthesizer (Click for more info)
  • Clock multipliers play a key role in design of high-speed electrical and optical links. As the aggregate bandwidth requirement for chip-to-chip interconnects grows, their respective frequency of operation increases. In this project a first order frequency synthesizer is presented that is suitable for high-speed on-chip clock generation. In this architecture the rising edge of the reference clock is directly injected to the output clock, resetting jitter accumulation similar to an MDLL.

  • Wideband Injection Locking and Quadrature Phase Generation
  • Injection-locked-oscillators (ILOs) have been used extensively because of their simple implementation and instantaneous locking characteristics. However, their application is hindered by their limited locking range compared with alternative techniques such as PLLs. In this project, PLL and injection locking elements are combined symbiotically to achieve wide locking range while retaining the simplicity of the latter.

  • On-Chip Interconnects (Click for more info)
  • Our goal in this project is to take a close look at on-chip wires scaling and investigate the challenges of on-chip signaling in highly-scaled technologies. Novel techniques to mitigate these challenges in a power and area efficient manner are introduced.

  • Network-on-Chip Architectures (Click for more info)
  • Network-on-chip (NoC) allows regular layout and hierarchical design, enabling high-core-count system-on-chip (SoC) designs that are capable of addressing future computational demands and challenges. We are investigating architectural and circuit-level approaches to enable the next-generation of efficient, high-performance computing systems.


 © California Institute of Technology