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Network-on-Chip Architectures
Team member: Matthew Loh

As integrated circuit wire densities increase to support ever-smaller transistor geometries, full-swing global interconnect and clock distribution becomes prohibitively expensive in power, delay and reliability. To overcome this limitation, future designs will increasingly rely on a network-on-chip (NoC) design paradigm. This approach allows regular layout and hierarchical design, enabling high-core-count system-on-chip (SoC) designs that are capable of addressing future computational demands and challenges.

NoC designs face several challenges beyond raw bandwidth. They will need to interface many heterogenous cores, or homogenous cores operating at different frequencies as a result of dynamic voltage and frequency scaling (DVFS). This creates a synchronization problem at the interface between these cores. If the interface clock is too slow, communication bandwidth is restricted. Conversely, if the clock is too high, cycles (therefore power) will be wasted communicating with cores operating at a lower speed. DVFS makes this more challenging, since the clock frequency of the cores will be changing rapidly, and a fixed interface clock may therefore not be the right solution.

Additionally, to ease the challenge of programming many-core systems, the latency of communication needs to be both low and consistent - ideally, it should not take any longer to communicate between cores on opposite sides of the chip as between cores which are adjacent to each other. To approach this ideal, long-distance wires will be required. Traditional repeater-based design is power and area inefficient, and imposes steeper penalties as wire densities increase.

We are investigating architectural and circuit-level approaches to address these challenges and enable the next-generation of efficient, high-performance computing systems.

 © California Institute of Technology