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Optical Chip-to-Chip Links in CMOS
Team member: Meisam Honarvar Nazari


Integrated circuit scaling has enabled a huge growth in processing power, which necessitates a corresponding increase in inter-chip communication bandwidth. This trend is expected to continue, requiring both an increase in the per-pin data rate and the I/O count. Unfortunately the bandwidth of the electrical channels used for inter-chip communication has not scaled in the same manner. A promising solution to this I/O bandwidth problem is the use of optical inter-chip communication links. The negligible frequency dependent loss of optical channels provides the potential for optical link designs to fully leverage increased data rates provided through CMOS technology scaling without excessive equalization complexity. In this project, a dense, low-power optical receiver is developed in 65 nm CMOS employing double sampling technique which is capable of operating up to 20 Gb/s.

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